Crossbar Resistive RAM (ReRAM) Code and Data memory IP cores are an ideal choice for embedded applications such as Internet of Things (IoT), wearables, tablets, smartphones, consumer electronics, artificial intelligence, industrial, automotive and medical. They enable the integration of non-volatile memory IP cores at the same process nodes of micro-controllers (MCU), System-on-Chip (SoC) and Field Programmable Gate Arrays (FPGA) from 40nm to 28nm.

The Crossbar ReRAM IP cores offer a cost effective integrated memory solution for embedded applications requiring low latency, high performance and low power nonvolatile code execution and data storage by improving system performance and reducing the complexity of today’s Flash-based IP cores or solutions. The IP cores are provided to customers as hard macros. Supported densities can be customized, range from 2M bits (256K Bytes) to 128M bits (16M Bytes), or custom size.

Embedded ReRAM Memory IP Features

  • Embedded 1T1R memory IP cores
  • 2M bits (256KB) to 128M bits(16MB) densities, or custom size
  • 40nm and 28nm standard CMOS process nodes
  • Synchronous primary interface: clock: 40MHz; 32bits data in, 32bits data out
  • Supply voltage (40nm): VDD=1.1V (+10%, -5%); VDDH=1.5V (±10%)
  • No erase required prior to write
  • Status register: tracks ready/busy and success/failure
  • Outputs for ready/busy and pass/fail
  • Write protection to prevent inadvertent writes
  • Write endurance – 100K write cycles
  • Retention – 10 years at 85°C (post 10K cycles)

Deliverables List

  • Front-end: LEF model, behavior model, timing model
  • Back-end: GDSII, DRC&LVS report, PIPO log
  • Collaterals:
    • Datasheet
    • Test methodology guide
    • Integration guide
    • Application notes
    • Evaluation board

Customer Support