Every hardware wallet on the market today is built on borrowed silicon — general-purpose chips stitched together and asked to do a job they were never designed for. Crossbar built Daric (internal codename of CrossBar Chip 1) to change that: the first chip designed from the ground up to secure digital assets.
1. The Wallet Chip Dilemma
Crypto wallets have historically been forced to choose between two kinds of off-the-shelf parts. A microcontroller (MCU) brings flexibility and real compute power, but lacks physical security — it can be glitched, probed, or re-flashed with malicious firmware. A secure element (SE) brings hardened tamper resistance, but runs on a tiny, decades-old core (typically an ARM M0–M3 at 50–70 MHz) with no support for modern blockchain cryptography.
Wallet makers bolt the two together — and inherit the weaknesses of both. In a typical design the SE is used as little more than secure storage, while the private key is reconstituted and signed on the less-protected MCU. Worse, the two chips talk over an exposed I²C or SPI bus that an attacker can snoop or manipulate, and the entire user interface — the display showing the address, the buttons confirming the transaction — runs outside the secure boundary. The result is a long list of proven attack surfaces: low-entropy key generation, fraudulent address display, firmware substitution, and counterfeit chips slipped in through the supply chain.
Daric collapses the MCU, the secure element, and everything in between onto a single die — all under one shield.
2. What Is a Secure Processing Unit?
Crossbar’s answer is a new category of chip: the Secure Processing Unit (SPU). Built on TSMC’s 22 nm ultra-low-leakage (ULL) process with embedded ReRAM, Daric integrates an 800 MHz ARM Cortex-M7 processor, a 400 MHz open-source RISC-V processor with MMU support, 4 MB of ReRAM, 2 MB of SRAM, an isolated cryptographic engine, integrated power management, hardware random number generation, and rich peripheral interfaces — including USB 2.0, SDIO, SPI, I²C, UART, camera, and QSPI — onto a single protected die. Physical and logical countermeasures extend across the entire chip, eliminating exposed inter-chip buses and allowing developers to build a complete secure wallet platform on one trusted silicon foundation.
3. Two Processors, Room to Build
Unlike the cramped core inside a conventional secure element, Daric carries two full processors. The primary is a 32-bit ARM Cortex-M7 running at 800 MHz — the most capable core in ARM’s M-series. Equipped with a double-precision floating-point unit (FPU), memory protection unit (MPU), 16 KB instruction and data caches, tightly coupled memory, and roughly 1,027 DMIPS of compute performance, it provides ample headroom to execute modern wallet software, advanced blockchain protocols, and responsive user interfaces entirely inside the secure boundary.
Alongside it sits an open-source 400 MHz RISC-V processor (VexRiscv) with a true memory management unit (MMU), enabling memory virtualization and stronger software isolation while supporting operating systems such as Xous. This capability is rarely found in secure microcontrollers and gives developers greater flexibility in structuring secure applications.
4. Memory That Can’t Be Read
Both processors and the cryptographic engine store their code and secrets in 4 MB of on-chip ReRAM (Resistive RAM), backed by 2 MB of SRAM. This is a deliberate security choice. Unlike the floating-gate flash used in conventional MCUs and secure elements, which stores data as trapped electric charge that can gradually leak over time and may be observed through advanced physical attacks such as passive voltage contrast or electron microscopy, ReRAM stores information by changing material resistance rather than electrical charge.
As a result, ReRAM offers long-term data retention, greater resilience to magnetic fields and radiation, and stronger resistance to physical extraction techniques. Because ReRAM can also be integrated into an advanced 22 nm ULL manufacturing process, Daric combines substantially larger on-chip memory with a finer-pitch active mesh and lower electromagnetic emissions, making both data storage and the chip’s physical countermeasures more difficult to attack.
Optional dual-QSPI interfaces provide additional application storage when required, while security-critical code, cryptographic keys, and persistent data remain protected inside the secure boundary. This architecture allows developers to expand application capacity without moving sensitive assets outside the protected chip.
5. A Crypto Accelerator Built for Blockchains
For a hardware wallet, the cryptographic engine is the product — and Daric’s is a self-contained subsystem isolated from the application processors through dedicated hardware, secure DMA, protected memory, and controlled interfaces. It includes dedicated secure memory and hardware access controls that keep cryptographic keys within the protected subsystem throughout their lifecycle. Cryptographic operations can be chained together directly inside the engine without exposing intermediate secrets to application software, reducing software attack surfaces while maintaining hardware-enforced isolation.
The engine provides hardware acceleration for a broad range of modern blockchain cryptography, including ECDSA, Schnorr, EdDSA, ECDH, X25519, Ristretto, RSA (up to 8192 bits), the Paillier homomorphic cryptosystem, AES-256, ChaCha20/Poly1305, SHA-2, SHA-3/Keccak, RIPEMD-160, BLAKE2, BLAKE3, HMAC, and hierarchical key derivation using PBKDF2 (BIP32-like) and SLIP-10. These capabilities enable developers to implement today’s major blockchain protocols and MPC-based applications while relying on dedicated hardware rather than software-only cryptography.
High-entropy keys are generated by Daric’s integrated hardware random number generator (RNG), while key derivation and cryptographic processing remain within the isolated cryptographic subsystem. By performing key generation, storage, and cryptographic operations inside dedicated hardware, Daric minimizes software exposure and reduces the attack surface for digital asset applications.
6. Defense In Depth
Because Daric is one chip, security can be enforced as a single, indivisible policy rather than negotiated across an exposed bus. Protection is layered from the silicon outward.
At the outermost layer, an active metal mesh of 64 monitored lines blankets the top of the die, detecting any attempt to decap or physically probe it and triggering an instant reset or key wipe. A dedicated safety unit watches for voltage glitches, laser and light injection, abnormal temperatures, and clock tampering, while side-channel defenses — power balancing and clock jitter — obscure the chip’s power signature during signing. Beneath that sits logical security: secure boot, lifecycle and debug-mode sealing, layered memory and peripheral protection units, ECC on critical memories, redundant key registers, puzzle routing, and on-alarm secret zeroization.
Tamper detection covers the processor, the crypto engine, and the ReRAM at once — so a single policy can wipe keys or lock the chip the instant an attack is sensed.
7. Trust from Foundry to UI
Integration also closes the supply-chain gap. Because Crossbar makes its own silicon, it can program serial numbers, certificates, and attestation keys directly on the factory floor — credentials that can be verified at any later stage, including by the end user. And because the SPU covers not just cryptography but trusted user interaction, user input, and the display, that provenance extends across every function of the device, from foundry to user interface. The exposed inter-chip bus, insecure trust boundaries between chips, and many opportunities for firmware substitution or counterfeit-component attacks that plague traditional two-chip wallet designs are eliminated by the SPU architecture.
Finally, Daric breaks with the “security by obscurity” tradition of incumbent secure-element vendors: it is open silicon, with full RTL published on GitHub and an open development kit. Security that can be inspected is security that can be trusted. Learn more in the Daric SDK and Daric Hardware on GitHub.
8. Daric: A New Foundation for Secure Hardware
Daric is the first member of Crossbar’s Secure Processing Unit line and is already being integrated into the company’s PHSM product line, with the next-generation Denarius under development. More importantly, it represents a shift in how secure hardware is designed. Rather than combining a general-purpose MCU with a separate secure element, Daric integrates computing, cryptography, secure memory, secure I/O, and layered physical protection into a single tamper-resistant platform.
For wallet manufacturers, custody providers, and embedded security developers, this means fewer attack surfaces, lower system complexity, and the freedom to build richer applications without compromising hardware trust. Instead of assembling security from multiple chips, Daric makes the Secure Processing Unit itself the trusted computing foundation for digital assets.
— The CrossBar Team